/******************************************************************************
*
*    File Name:  Assertion.sv
*      Version:  1.0
*         Date:  June 13th, 2013
*        Model:  
*    Simulator:  Questa Sim- Mentor Graphics (Version 64 10.2a)
*
* Dependencies:  DDRInterface.sv
*
*       Author:  Nachiket Khasbag & Nikhil Patil 
*        Email:  nachiket@pdx.edu, pnikhil@gmail.com
*        Phone:  404-660-0757, 971-300-1728
*   University:  Portland State University
*
*
******************************************************************************/


import DDRStub::*;
`timescale 1ns/1ps

module assertion(clk, dqs, dq);
  
  input clk;
  output dqs;
  inout dq;  
  
  property DataStrobe;
    @(posedge clk)
       (dqs) |-> !($isunknown(dq));
    endproperty
    NoData: assert property(DataStrobe);
endmodule
